W90N740

Features: Architecture• Highly-integrated system for embedded Ethernet applications• Powerful ARM7TDMI core and fully 16/32-bit RISC architecture• Big /Little-Endian mode supported• Cost-effective JTAG-based debug solutionSystem Manager• System memory map &...

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W90N740: Features: Architecture• Highly-integrated system for embedded Ethernet applications• Powerful ARM7TDMI core and fully 16/32-bit RISC architecture• Big /Little-Endian mode s...

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Part Number:
W90N740
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

Architecture
• Highly-integrated system for embedded Ethernet applications
• Powerful ARM7TDMI core and fully 16/32-bit RISC architecture
• Big /Little-Endian mode supported
• Cost-effective JTAG-based debug solution
System Manager
• System memory map & on-chip peripherals memory map
• The data bus width of external memory address & data bus connection with external memory
• Bus arbitration supports the Fixed Priority Mode & Rotate Priority Mode
• Power-On setting
• On-Chip PLL module control & Clock select control
External Bus Interface (EBI)
• External I/O Control with 8/16/32 bit external data bus
• Cost-effective memory-to-peripheral DMA interface
• SDRAM Controller supports up to 2 external SDRAM & the maximum size of each device is 32MB
• ROM/FLASH & External I/O interface
• Support for PCMCIA 16-bit PC Card devices
On-Chip Instruction and Data Cache
• Two-way, Set-associative, 8K-byte I-cache and 2K-byte D-cache
• Support for LRU (Least Recently Used) Protocol
• Cache can be configured as an internal SRAM
• Support Cache Lock function
Ethernet MAC Controller (EMC)
• IEEE 802.3 protocol engine with programmable MII or RMII interface for 10/100 Mbits/s
• DMA engine with burst mode
• 256 bytes transmit & 256 bytes receive FIFO for MAC protocol engine and DMA access
• Built-in 16 entry CAM Address Register
• Support long frame (more than 1518 bytes) and short frame (less than 64 bytes)
• Re-transmit (during collision) the frame without DMA access
• Half or full duplex function option
• Support Station Management for external PHY
• On-Chip Pad generation
NAT Accelerator (Patent Pending)
• Hardware acceleration on IP address / port number look up and replacement for network address translation, including MAC address translation
• Provide 64 entries of translation table
• Support TCP / UDP packets
GDMA Controller
• 2 Channel GDMA for memory-to-memory data transfers without CPU intervention
• Increase or decrease source / destination address in 8-bit, 16-bit, or 32-bit data transfers
• Supports 4-data burst mode to boost performance
• Support external GDMA request
USB Host Controller
• USB 1.1 compatible
• Open Host Controller Interface (OHCI) 1.0 compatible.
• Supports both low-speed (1.5 Mbps) and full-speed (12Mbps) USB devices.
• Built-in DMA for real-time data transfer
UART
• One UART (serial I/O) blocks with interrupt-based operation
• Full set of MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
• Fully programmable serial-interface characteristics:
• Break generation and detection
• False start bit detection
• Parity, overrun, and framing error detection
• Full prioritized interrupt system controls
Timers
• Two programmable 24-bit timers with 8-bit pre-scalar
• One programmable 24-bit Watch-Dog timer
• One-short mode, period mode or toggle mode operation
Programmable I/Os
• 21 programmable I/O ports
I• /O ports Configurable for Multiple functions
Advanced Interrupt Controller (AIC)
• 18 interrupt sources, including 4 external interrupt sources
• Programmable normal or fast interrupt mode (IRQ, FIQ)
• Programmable as either edge-triggered or level-sensitive for 4 external interrupt sources
• Programmable as either low-active or high-active for 4 external interrupt sources
• Priority methodology is encoded to allow for interrupt daisy-chaining
• Automatically mask out the lower priority interrupt during interrupt nesting
GPIO Controller
• Programmable as an input or output pin
On-Chip PLL
• One PLL for both CPU and USB host controller
• The external clock can be multiplied by on-chip PLL to provide high frequency system clock
• Programmable clock frequency, and the input frequency range is 3-30MHz; 15MHz is preferred.
Operation Voltage Range
• 2.7 3.6 V for IO Buffer
• 1.62 1.98 V for Core Logic
Operation Temperature Range
• 0 70 Degree C
Operating Frequency
• 80 MHz (default)
Package Type
• 176-pin LQFP



Pinout

  Connection Diagram


Specifications

Ambient Temperature ...................................................................
Storage Temperature ........................................................................
Voltage on Any Pin ...........................................................................
Power Supply Voltage (Core logic) ..................................................
Power Supply Voltage (IO Buffer) ...................................................
Injection Current (latch-up testing) ...................................................
Crystal Frequency ....................................................................



Description

The W90N740 micro-controller is 16/32 bit, ARM7TDMI based RISC micro-controller for network as well as embedded applications. An integrated dual Ethernet MAC, the W90N740, is designed for use in broadband routers, wireless access points, residential gateways and LAN camera.
The W90N740N is built around The ARM7TDMI CPU core designed by Advanced RISC Machines, Ltd. And achieves 80MHz under worse conditions. Its small size, fully static design is particularly suitable for cost-sensitive and power-sensitive applications. W90N740 designs as Harvard architecture by offering an 8K-byte I-cache/SRAM and an 2K-byte D-cache/SRAM with flexible configuration and two way set associative structure to balance data movement between CPU and external memory. Four stages write buffer also improves latency for write operations.
The external bus interface (EBI) controller provides single bus architecture, 8/16/32 bit data width to access external SDRAM, ROM/SRAM, flash memory and I/O devices. It achieves same frequency as CPU core to minimize latency if internal cache misses. Memory controller supports different kinds of SDRAM types and configurations to ease system design. The System Manager includes an internal 32-bit system bus arbiter and a PLL clock controller. Generic I/O bus is easily served as PCMCIA-like interface for 802.11b wireless LAN connection.
Two 10/100Mb MACs of Ethernet controller is built in to reduce total system cost and increase performance between WAN and LAN port. Either MII or RMII of MAC is selected for external 10/100 PHY chip to design for varieties of applications. A powerful NAT accelerator (Patent Pending) between LAN and WAN reduces the software loading of CPU and speeds up performance between LAN and WAN.
W90N740 integrates root hub of USB 1.1 host controller with one port transceiver and uses additional port with xternal transceiver if necessary, which can add valuable functions like flash disk, printer server, Bluetooth device via  SB port. The important peripheral functions include one full wired high speed UART channel, 2-Channel GDMA, one  watch-dog timer, two 24-bit timers with 8-bit pre-scale, 20 programmable I/O ports, and an advanced interrupt  ontroller.




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