W83L177R

Features: · 10 SDRAM clocks for 2-DIMMs· Clock skew less than 250ps· Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay)· I2C 2-wire serial interface· Programmable registers to enable/stop each output· Incorporate with W83L197R-16· 28pin-SOP package (209mil)PinoutSpeci...

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W83L177R Picture
SeekIC No. : 004545218 Detail

W83L177R: Features: · 10 SDRAM clocks for 2-DIMMs· Clock skew less than 250ps· Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay)· I2C 2-wire serial interface· Programmable regis...

floor Price/Ceiling Price

Part Number:
W83L177R
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/20

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Product Details

Description



Features:

·  10 SDRAM clocks for 2-DIMMs
·  Clock skew less than 250ps
·  Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay)
·  I2C 2-wire serial interface
·  Programmable registers to enable/stop each output
·  Incorporate with W83L197R-16
·  28pin-SOP package (209mil)



Pinout

  Connection Diagram


Specifications

Symbol

PARAMETER

RATING
Vdd , VIN
Voltage on any pin with respect to GND
-0.5V to +7.0V
TSTG
Storage Temperature
-65° C to +150° C
TB
Ambient Temperature
-55° C to +125° C

TA

Operating Temperature

0°C to + 70°C




Description

The W83L177R is a 10 outputs SDRAM clock buffer for 2-DIMMs models incorporate with W83L197R-16 which is the clock synthesizer especially for the 100MHz models such as Intel BX chipsets.(Refer the datasheet fo Winbond W83L197R-16)

The W83L177R receives the clock from chipset by the Buffer_In pin and provides almost zerodelay (less than 4ns propagation delay) SDRAM buffer outputs for the 10 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83L197R-16. The clock skew between any two clock outputs is less than 250ps and the output buffer impedance is about 15 ohms.

The W83L177R also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs.




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