W49V002F

The W49V002F is a 2-megabit, 3.3-volt only CMOS flash memory organized as 256K x 8 bits.The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49V002F results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers.

The W49V002F has the following features include:(1)fast erase operation: 150 mS (typ.);(2)fast read access time: Tkq 11 nS;(3)endurance: 10K cycles (typ.);(4)twenty-year data retention;(5)hardware data protection;(6)one 16K bytes boot block with lockout protection;(7)two 8K bytes parameter blocks;(8)four main memory blocks (with 32K bytes,64K bytes, 64K bytes, 64K bytes each);(9)latched address and data;(10)TTL compatible I/O;(11)available packages: 32-pin-PLCC, 32-pin TSOP.See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method.

The absolute maximum ratings of the W49V002F are:(1)power supply voltage to Vss potential:-0.5 to +4.1V;(2)storage temperature:-65 to +150;(3)operating temperature:0 to +70;(4)D.C. voltage on any pin to ground potential:-0.5 to Vdd+0.5.The W49V002F includes a data polling feature to indicate the end of a program or erase cycle.When the W49V002F is in the internal program or erase cycle, any attempts to read DOS of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle,and when erase cycle has been completed it becomes logical "1"or true data.The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 150 mS (typical). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory blocks will be erased to FF(hex) while the data in the boot block will not (remains as the same state before the chip erase operation).