W3H32M72E-XSBX

` Data rate = 667*, 533, 400
` Package:
• 208 Plastic Ball Grid Array (PBGA), 18 x 20mm
• 1.0mm pitch
` Differential data strobe (DQS, DQS#) per byte
` Internal, pipelined, double data rate architecture
` 4-bit prefetch architecture
` DLL for alignment of DQ and DQS transitions with clock signal
` Four internal banks for concurrent operation (Per DDR2 SDRAM Die)
` Programmable Burst lengths: 4 or 8
` Auto Refresh and Self Refresh Modes
` On Die Termination (ODT)
` Adjustable data output drive strength
` Single 1.8V ±0.1V supply
` Programmable CAS latency: 3, 4, 5, or 6
` Posted CAS additive latency: 0, 1, 2, 3 or 4
` Write latency = Read latency - 1* tCK
` Commercial, Industrial and Military Temperature Rang es
` Organized as 32M x 72
` Weight: W3H32M72E-XSBX - 2.5 grams typical

The 2Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory containing 2,147,483,648 bits.

Each of the fi ve ships in the MCP are internally confi gured as 4-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3.

The 2Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the 2Gb DDR2 SDRAM effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. There are strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#).

The 2Gb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.

Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read or write burst lengths of four or eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another read, or a burst write of eight with another write.

An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time.

A self refresh mode is provided, along with a power-saving power-down mode.

All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength outputs are SSTL_18- compatible.