W3H32M64E-XSBX

·Data rate = 667*, 533, 400
·Package:
                ·208  Plastic Ball Grid Array (PBGA), 16 x 20mm
                ·1.0mm pitch
·DDR2 Data Rate = 667*, 533, 400
·Supply Voltage = 1.8V±0.1
·Differential data strobe (DQS, DQS#) per byte
·Internal, pipelined, double data rate architecture
·4-bit prefetch architecture
·DLL for alignment of DQ and DQS transitions with clock signal
·Four internal banks for concurrent operation (Per DDR2 SDRAM Die)
·Programmable Burst lengths: 4 or 8
·Auto Refresh and Self Refresh Modes
·On Die Termination (ODT)
·Adjustable data C output drive strengt
·Programmable CAS latency:  3, 4 or 5
·Posted CAS additive latency:  0, 1, 2, 3 or 4
·Write latency = Read latency - 1* tCK
·Commercial, Industrial and Military Temperature Rang es
·Organized as 32M x 64, user con gurable as 2 x 32M x 32
·Weight: W3H32M64E-XSBX - 2.5 grams typical