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W3EG72129S-JD3

Features: · Double-data-rate architecture· Clock speeds of 100MHz, 133MHz, 166MHz and 200MHz· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2,5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & in...

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SeekIC No. : 004544719 Detail

W3EG72129S-JD3: Features: · Double-data-rate architecture· Clock speeds of 100MHz, 133MHz, 166MHz and 200MHz· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Late...

W3EG72129S-JD3 Data Sheet

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Part Number:
W3EG72129S-JD3
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

· Double-data-rate architecture
· Clock speeds of 100MHz, 133MHz, 166MHz and 200MHz
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2,5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detect
· Dual Rank
· Power Supply:
• VCC = VCCQ = +2.5V (100, 133 and 166MHz)
• VCC = VCCQ = +2.6V (200MHz)
· JEDEC standard 184 pin DIMM package
· PCB height:
• JD3: 30.48mm (1.20")


Specifications

Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VO -0.5 to 3 V
Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V
Storage Temperature TSTG -55 to +150 °C
Power Dissipation PD 18 W
Short Circuit Current IOS 50 mA
Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliabili


Description

The W3EG72129S-JD3  is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eighteen 64Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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