Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JEDEC design specifi cation• Bi-directional data strobes (DQS)• Differential clock inputs (CK & CK#)• Programmable Read Latency 2,2.5 (clock)• Programmable Burst Length (2,4,8)...
W3EG128M72ETSU-AJD3: Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JEDEC design specifi cation• Bi-directional data strobes (DQS)• Differential clock inputs ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: · Double-data-rate architecture· Clock speeds of 133MHz and 166MHz· Bi-directional data ...
Parameter |
Symbol |
Value |
Units |
Voltage on any pin relative to VSS |
VIN, VOUT |
0.5 ~ 3.6 |
V |
Voltage on VCC supply relative to VSS |
VCC, VCCQ |
1.0 ~ 3.6 |
V |
Storage Temperature |
TSTG |
55 ~ +150 |
|
Power Dissipation |
PD |
9 |
W |
Short Circuit Current |
IOS |
50 |
mA |
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
The W3EG128M72ETSU is a 128Mx72 Double Data Rate SDRAM memory module based on 1Gb DDR SDRAM components. The module consists of nine 128Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.