Features: · Double-data rate architecture· DDR200, DDR266, DDR333 and DDR400 • JEDEC design specifi cations· BI-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (seque...
W3EG72128S-D3: Features: · Double-data rate architecture· DDR200, DDR266, DDR333 and DDR400 • JEDEC design specifi cations· BI-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Progra...
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Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Parameter |
Symbol |
Ratings |
Unit |
Voltage on any pin relative to VSS |
VIN, VOUT |
-0.5 to 3.6 |
V |
Voltage on VCC supply relative to VSS |
VCC, VCCQ |
-1.0 to 3.6 |
V |
Storage Temperature |
TSTG |
-55 to +150 |
°C |
Power Dissipation |
PD |
18 |
W |
Short Circuit Current |
IOS |
50 |
mA |
The W3EG72128S is a 2x64Mx72 Double data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eighteen 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precisse cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.