Features: •Double-data-rate architecture•DDR200, DDR266 and DDR333:• JEDEC design specifi cations•Bi-directional data strobes (DQS)•Differential clock inputs (CK & CK#)•Programmable Read Latency 2,2.5 (clock)•Programmable Burst Length (2,4,8)R...
W3EG72126S-D3: Features: •Double-data-rate architecture•DDR200, DDR266 and DDR333:• JEDEC design specifi cations•Bi-directional data strobes (DQS)•Differential clock inputs (CK ...
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Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Parameter |
Symbol |
Value |
Units |
Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS |
VIN, VOUT VCC, VCCQ |
-0.5 to 3.6 -1.0 to 3.6 |
V V |
Storage Temperature Power Dissipation Short Circuit Current |
TSTG PD IOS |
-55 to +150 27 50 |
W mA |
The W3EG72126S-D3 is a 128Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The W3EG72126S-D3 consists of eighteen 128Mx4 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.