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W3EG6467S

Features: · DDR200, DDR266, DDR333 and DDR400-JEDEC design specifi cations· Double-data-rate architecture· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential &a...

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SeekIC No. : 004544712 Detail

W3EG6467S: Features: · DDR200, DDR266, DDR333 and DDR400-JEDEC design specifi cations· Double-data-rate architecture· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable R...

W3EG6467S Data Sheet

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Part Number:
W3EG6467S
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

· DDR200, DDR266, DDR333 and DDR400
- JEDEC design specifi cations
· Double-data-rate architecture
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detect
· Dual Rank
· Power supply: 2.5V ± 0.20V
· 200 pin SO-DIMM package
- Package height options


Specifications

Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-0.5 to 3.6
V
Storage Temperature
TSTG
-55 to +150
Power Dissipation
PD
8
W
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The W3EG6467S is a 2x32Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eight 32Mx16 DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data 1/0 transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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