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W3EG6464S-JD3-D3

Features: · Double-data-rate architecture· DDR200 and DDR266 • JEDEC design specifi cation· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & inter...

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SeekIC No. : 004544710 Detail

W3EG6464S-JD3-D3: Features: · Double-data-rate architecture· DDR200 and DDR266 • JEDEC design specifi cation· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Laten...

W3EG6464S-JD3-D3 Data Sheet

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Part Number:
W3EG6464S-JD3-D3
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

· Double-data-rate architecture
· DDR200 and DDR266
   • JEDEC design specifi cation
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input.
· Auto and self refresh
· Serial presence detect
· Power supply: VCC: 2.5V ± 0.20V
· JEDEC standard 184 pin DIMM package
   • Package height option:  JD3: 30.48mm (1.20")


Specifications

Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V
Voltage on VCC supply relative to VSS VCC,VDDQ -1.0 to 34.6 V
Storage Temperature TSTG -55 to +150
Power Dissipation PD 8 W
Short Circuit Current IOS 50 mA

Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The W3EG6464S is a 64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of eight 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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