W3EG6464S-AD4

Features:

· Double-data-rate architecture
· Speeds of 100MHz, 133MHz and 166MHz
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detect
· Power supply: VCC: 2.5V ± 0.2V
· JEDEC standard 200 pin SO-DIMM package
    · Package height options:
        AD4: 35.5 mm (1.38"),
        BD4: 31.75 (1.25")



Specifications

Parameter	Symbol	Value	Units
Voltage on any pin relative to VSS	VIN, VOUT	-0.5 to 3.6	V
Voltage on VCC supply relative to VSS	VCC, VCCQ	-1.0 to 3.6	V
Storage Temperature	TSTG	-55 to +150
Power Dissipation	PD	8	W
Short Circuit Current	IOS	50	mA

Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The W3EG6464S is a 64Mx64 Double Data Rate SDRAM mem o ry module based on 512Mb DDR SDRAM component. The module consists of eight 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.