Features: Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400• JEDEC design specifi edBi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & in...
W3EG6462S-D3: Features: Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400• JEDEC design specifi edBi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read ...
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Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Features: • Double-data-rate architecture• DDR200, DDR266, DDR333 and DDR400• JE...
Parameter | Symbol | Value | Units |
Voltage on any pin relative to VSS | VIN, VOUT | -0.5 to 3.6 | V |
Voltage on VCC supply relative to VSS | VCC, VCCQ | -1.0 to 3.6 | A |
Storage Temperature | TSTG | 250 | |
Power Dissipation | PD | 30 | |
Short Circuit Current | IOS | - 65 to 175 |
Note:
Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
The W3EG6462S is a 2x32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of sixteen 32Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.
Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.