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W3EG64255S-JD3

Features: · Double-data-rate architecture·DDR200, DDR266 and DDR333; • JEDEC design specifi cations·Bi-directional data strobes (DQS)·Differential clock inputs (CK & CK#)·Programmable Read Latency 2,2.5 (clock)·Programmable Burst Length (2,4,8)·Programmable Burst type (sequential &...

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SeekIC No. : 004544701 Detail

W3EG64255S-JD3: Features: · Double-data-rate architecture·DDR200, DDR266 and DDR333; • JEDEC design specifi cations·Bi-directional data strobes (DQS)·Differential clock inputs (CK & CK#)·Programmabl...

W3EG64255S-JD3 Data Sheet

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Part Number:
W3EG64255S-JD3
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/21

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Product Details

Description



Features:

· Double-data-rate architecture
· DDR200, DDR266 and DDR333;
    • JEDEC design specifi cations
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input.
· Auto and self refresh
· Serial presence detect
· Dual Rank
· Power supply: VCC 2.5V ± 0.2V
· JEDEC standard 184 pin DIMM package
    • JD3: 30.48 (1.20")

NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option


Specifications

Parameter

Symbol

Value

Units

Voltage on any pin relative to VSS

VIN, VOUT

-0.5 - 3.6

V

Voltage on VCC supply relative to VSS

VCC, VCCQ

-1.0 - 3.6

V

Storage Temperature

TSTG

-55 - +150

Power Dissipation

PD

27

W

Short Circuit Current

I0S

50

mA


Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
          Functional operation should be restricted to recommended operating condition.
          Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The W3EG64255S-JD3 is a 2x128Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The W3EG64255S-JD3 consists of sixteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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