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W3EG6418S-JD3

Features: Double-data-rate architecture DDR200 and DDR266• JEDEC design specifi cations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) ...

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SeekIC No. : 004544700 Detail

W3EG6418S-JD3: Features: Double-data-rate architecture DDR200 and DDR266• JEDEC design specifi cations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,...

W3EG6418S-JD3 Data Sheet

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Part Number:
W3EG6418S-JD3
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

Double-data-rate architecture
DDR200 and DDR266
• JEDEC design specifi cations
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Serial presence detect
Power Supply: 2.5V ± 0.20V
 JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48mm (1.20") MAX


Specifications

Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
 -1.0 to 3.6
V
Storage Temperature
TSTG
 -55 to +150
Power Dissipation
PD
8
W
Short Circuit Current
IOS
50
mA



Description

The W3EG6418S-JD3 is a 16Mx64 Double Data Rate SDRAM memory module based on 128Mb DDR SDRAM components. The W3EG6418S-JD3 consists of eight 16Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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