W3EG64129S-D3

· Clock speeds of 100MHz and 133MHz
· Double-data-rate architecture
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2,5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detect
· Power Supply: 2.5V ± 0.20V
· JEDEC standard 184 pin DIMM package

The W3EG64129S-D3 is a 124Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The W3EG64129S-D3 consists of sixteen 128Mx4 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.