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W3EG64128S

Features: • Double-data-rate architecture• Bi-directional data strobes (DQS)• Differential clock inputs (CK & CK#)• Programmable Read Latency 2,2.5 (clock)• Programmable Burst Length (2,4,8)• Programmable Burst type (sequential & interleave)• Edge ...

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SeekIC No. : 004544695 Detail

W3EG64128S: Features: • Double-data-rate architecture• Bi-directional data strobes (DQS)• Differential clock inputs (CK & CK#)• Programmable Read Latency 2,2.5 (clock)• Program...

W3EG64128S Data Sheet

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Part Number:
W3EG64128S
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/22

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Product Details

Description



Features:

• Double-data-rate architecture
• Bi-directional data strobes (DQS)
• Differential clock inputs (CK & CK#)
• Programmable Read Latency 2,2.5 (clock)
• Programmable Burst Length (2,4,8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto and self refresh
• Serial presence detect
• Dual Rank
• Power supply: 2.5V ± 0.2V
• JEDEC standard 200 pin SO-DIMM package
   -Package height options:
   BD4: 31.75 mm (1.25")


Specifications

Parameter Symbol Value Units
Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V
Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 ~ 3.6 V
Storage Temperature TSTG -55 ~ +150  
Power Dissipation PD 9 W
Short Circuit Current IOS 50 mA

Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.




Description

The W3EG64128S is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The W3EG64128S consists of eight 128Mx8 stack DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions.




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