W3EG264M72AFSR265D3xG

Features:

· Double-data-rate architecture
· DDR200, DDR266 and DDR333:
    • JEDEC design specifi cations
· Phase-lock loop (PLL) clock driver to reduce loading
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input
· Auto and self refresh
· Serial presence detect
· Dual Rank
· Power supply: V_CC 2.5V ± 0.2V
· JEDEC standard 184 pin DIMM package
    • Package height option: Low-profi le: 30.48mm (1.20")
    • Consult factory for availability of lead-free products.


Specifications

Parameter	Symbol	Value	Units
Voltage on any pin relative to VSS	VIN, VOUT	-0.5 to 3.6	V
Voltage on VCC supply relative to VSS	VCC, VCCQ	-1.0 to 3.6	V
Storage Temperature	TSTG	-55 to +150
Power Dissipation	PD	9	W
Short Circuit Current	IOS	50	mA

Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
          Functional operation should be restricted to recommended operating condition.
          Exposure to higher than recommended voltage for extended periods of time could affect device reliability.


Description

The W3EG264M72AFSR265D3xG is a 2x64Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The W3EG264M72AFSR265D3xG consists of thirtysix 64Mx4, in FBGA packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance
memory system ap pli ca tions.

* This W3EG264M72AFSR265D3xG is under development, is not qualifi ed or characterized and is subject to change or
   cancellation  without notice.