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W3EG2256M72ASSR-JD3

Features: · Double-data-rate architecture· DDR200, and DDR266:• JEDEC design specifi cations· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Latency 2,2.5 (clock)· Programmable Burst Length (2,4,8)· Programmable Burst type (sequential & int...

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SeekIC No. : 004544686 Detail

W3EG2256M72ASSR-JD3: Features: · Double-data-rate architecture· DDR200, and DDR266:• JEDEC design specifi cations· Bi-directional data strobes (DQS)· Differential clock inputs (CK & CK#)· Programmable Read Lat...

W3EG2256M72ASSR-JD3 Data Sheet

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Part Number:
W3EG2256M72ASSR-JD3
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/30

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Product Details

Description



Features:

· Double-data-rate architecture
· DDR200, and DDR266:
• JEDEC design specifi cations
· Bi-directional data strobes (DQS)
· Differential clock inputs (CK & CK#)
· Programmable Read Latency 2,2.5 (clock)
· Programmable Burst Length (2,4,8)
· Programmable Burst type (sequential & interleave)
· Edge aligned data output, center aligned data input.
· Auto and self refresh
· Serial presence detect
· Dual Rank
· Power supply: VCC = 2.5V ± 0.2V
· JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.2"),
AJD3: 28.70mm (1.13")


Specifications

Parameter Symbol Value Units
Voltage on Any Pin Relative to Vss VIN ,OUT -0.5 - 3.6 V
Voltage on Vcc Supply Relative to Vss Vcc -1.0 - 3.6 V
Power Dissipation PD -55 - +150
Storage Temperature TSTG 27 W
Short Circuit Output Current IOS 50 mA
Note: Permanent device damage may occur if 'ABSOLUTE MAXIMUM RATINGS' are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability


Description

The W3EG2256M72ASSR is a 2x256Mx72 Double Data Rate SDRAM memory module based on 1Gb DDR SDRAM components. The module consists of eighteen 512Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.




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