Features: DDR SDRAM rate = 200, 250, 266, 333Mb/sPackage:• 219 Plastic Ball Grid Array (PBGA),25mm x 25mm, 625mm22.5V ±0.2V core power supply2.5V I/O (SSTL_2 compatible)Differential clock in puts (CK and CK#)Commands entered on each positive CK edgeInternal pipelined double-data-rate (DDR) a...
W3E32M64S-XBX: Features: DDR SDRAM rate = 200, 250, 266, 333Mb/sPackage:• 219 Plastic Ball Grid Array (PBGA),25mm x 25mm, 625mm22.5V ±0.2V core power supply2.5V I/O (SSTL_2 compatible)Differential clock in p...
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Features: ·Data rate = 200, 250, 266, 333Mbs ·Package:-219 Plastic Ball Grid Array (PBGA), 32 x 25...
Features: ·Data rate = 200, 250, 266, 333Mbs·Package:• 208 Plastic Ball Grid Array (PBGA), 1...
Parameter | Unit | |
Voltage on VCC, VCCQ Supply relative to Vss | -1 to 3.6 | V |
Voltage on I/O pins relative to VSS | -1 to 3.6 | V |
Operating Temperature TA (Mil) | -55 to +125 | |
Operating Temperature TA (Ind) | -40 to +85 | |
Storage Temperature, Plastic | -55 to +125 |
NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. his is a stress rating only and func tion al op er a tion of the device at these or any other conditions greater than those in di cat ed in the operational sections of this specifi cation is not implied. Exposure to ab so lute maximum rating con di tions for extended periods may affect reliability.
The 256MByte (2Gb) DDR SDRAM W3E32M64S-XBX is a high-speed CMOS, dy nam ic ran dom-access, memory using 4 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM.
The 256MB DDR SDRAM W3E32M64S-XBX uses a double data rate ar chi tec ture to achieve high-speed operation. The double data rate ar chi tec ture is essentially a 2n-prefetch architecture with an in ter face designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256MB DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two cor re spond ing n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bi-directional data strobe (DQS) W3E32M64S-XBX is transmitted externally, along with data, for use in data capture at the receiver. strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. Each chip has two data strobes, one for the lower byte and one for the upper byte.
The 256MB DDR SDRAM W3E32M64S-XBX operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com mands (ad dress and control signals) are registered at every positive edge of CK. Input data is registered on both edg es of DQS, and out put data is ref er enced to both