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W25P243A

Features: · Synchronous operation· High-speed access time: 4.5/5/6 nS (max.)· Single +3.3V power supply· Individual byte write capability· 3.3V LVTTL compatible I/O· Clock-controlled and registered input· Asynchronous output enable· Pipelined data output capability· Supports snooze mode (low-power...

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SeekIC No. : 004544525 Detail

W25P243A: Features: · Synchronous operation· High-speed access time: 4.5/5/6 nS (max.)· Single +3.3V power supply· Individual byte write capability· 3.3V LVTTL compatible I/O· Clock-controlled and registered ...

W25P243A Data Sheet

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Part Number:
W25P243A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Synchronous operation
· High-speed access time: 4.5/5/6 nS (max.)
· Single +3.3V power supply
· Individual byte write capability
· 3.3V LVTTL compatible I/O
· Clock-controlled and registered input
· Asynchronous output enable
· Pipelined data output capability
· Supports snooze mode (low-power state)
· Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode
· Support 2T/1T mode
· Packaged in 128-pin QFP and TQFP


Pinout

Connection Diagram


Specifications

PARAMETER RATING UNIT
Core Supply Voltage to Vss -0.5 to +4.6 V
I/O Supply Voltage to Vss -0.5 to +4.6 V
Input/Output to VSS Potential VSSQ -0.5 to VDDQ +0.5 V
Allowable Power Dissipation 1.0 W
Storage Temperature -65 to +150 °C
Operating Temperature 0 to +70 °C




Description

The W25P243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 ´ 64 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentiumä burst mode and linear burst mode. The mode to be executed is controlled by the LBO pin. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduce power dissipation. W25P243A supports 2T/1T mode, while disable data output within one cycle in a burst read when the device is deselected by CE2/CE3 .




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