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W25P010A

Features: · Synchronous operation· High-speed access time: 6/7/8 nS (max.)· Single +3.3V power supply· Individual byte write capability· 3.3V LVTTL compatible I/O· Clock-controlled and registered input· Asynchronous output enable· Pipelined/non-pipelined data output capability· Supports snooze mod...

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SeekIC No. : 004544519 Detail

W25P010A: Features: · Synchronous operation· High-speed access time: 6/7/8 nS (max.)· Single +3.3V power supply· Individual byte write capability· 3.3V LVTTL compatible I/O· Clock-controlled and registered in...

W25P010A Data Sheet

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Part Number:
W25P010A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/20

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Product Details

Description



Features:

· Synchronous operation
· High-speed access time: 6/7/8 nS (max.)
· Single +3.3V power supply
· Individual byte write capability
· 3.3V LVTTL compatible I/O
· Clock-controlled and registered input
· Asynchronous output enable
· Pipelined/non-pipelined data output capability
· Supports snooze mode (low-power state)
· Internal burst counter supports Intel burst mode & linear burst mode
· Supports 2T/2T mode
· Packaged in 100-pin QFP and TQFP


Pinout

Connection Diagram


Specifications

PARAMETER
RATING
UNIT
Core Supply Voltage to Vss
-0.5 to 4.6
V
I/O Supply Voltage to VSS
-0.5 to 4.6
V
Input/Output to VSSQ Potential
VSSQ -0.5 to VDDQ +0.5
V
Allowable Power Dissipation
1.0
W
Storage Temperature
-65 to 150
Operating Temperature
0 to +70



Description

The W25P010A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 32,768 ´ 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentiumä burst mode and linear burst mode. The mode to be executed is controlled by the pin. Pipelining or non-pipelining of the data outputs is controlled by the

W25P010A support 2T/2T mode whcih will delay one cycle data output in a burst read cycle when the device is deselected by CE2 or CE3 . This mode supports 3-1-1-1-1-1-1-1 in a two-bank, back-toback burst read cycle.




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