Features: 3.3V supply operation Packaged in 16-pin SOIC & QSOP packages. Replaces separate VCXO and multiplier Uses inexpensive pullable crystal On-chip VCXO with 200 ppm pull range (±100 ppm) 5V-tolerant control inputs Zero ppm synthesis error in both clocksApplication• Telecom switchi...
VT83205: Features: 3.3V supply operation Packaged in 16-pin SOIC & QSOP packages. Replaces separate VCXO and multiplier Uses inexpensive pullable crystal On-chip VCXO with 200 ppm pull range (±100 ppm) ...
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Parameter |
Conditions |
Min |
Typ |
Max |
Units |
Supply voltage, VDD |
Referenced to GND |
|
|
5 |
V |
Inputs and Clock Outputs |
Referenced to GND |
-0.5 |
|
VDD+0.5 |
V |
Soldering Temperature |
Max of 10 seconds |
|
|
260 |
°C |
Storage temperature |
|
-65 |
|
150 |
°C |
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
The Vaishali VT83205 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 14.318 MHz, 30pF (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V control signal is used to fine tune the output clock frequency in the ±100ppm range. Select inputs SO:S2 are used for frequency and output selection.