VT83027

Features: 3.3V supply operation Low jitter PLL Clock Synthesizer Zero ppm synthesis error Uses inexpensive pullable crystal ±12mA drive capability On-chip oscillator with 200 ppm pull range (±100 ppm) 8 pin SOIC packageApplication Set-top boxes Telecom switching HDTV MPEG Video clock source...

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VT83027: Features: 3.3V supply operation Low jitter PLL Clock Synthesizer Zero ppm synthesis error Uses inexpensive pullable crystal ±12mA drive capability On-chip oscillator with 200 ppm pull range (±...

floor Price/Ceiling Price

Part Number:
VT83027
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

3.3V supply operation
Low jitter PLL Clock Synthesizer
  Zero ppm synthesis error
Uses inexpensive pullable crystal
±12mA drive capability
On-chip oscillator with 200 ppm pull range (±100 ppm)
8 pin SOIC package



Application

Set-top boxes
Telecom switching
HDTV
MPEG Video clock source



Pinout

  Connection Diagram


Specifications

Parameter
Conditions
Min
Typ
Max
Units
Supply voltage, VDD
Referenced to GND


6
V
Inputs and Clock Outputs
Referenced to GND
-0.5

VDD+0.5
V
Soldering Temperature
Max of 10 seconds


260
°C
Storage temperature

-65

150
°C


Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.




Description

The Vaishali VT83027 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 13.5 MHz, 14 pF (pull range of 200 ppm) crystal input, and produce a 27 MHz output. A 0 to 3V control signal is used to fine tune the output clock frequency in the ±100ppm range.




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