VS8061

The VS8061 has the following features including Serial Data Rate up to 2.5 Gb/s;16-bit Wide ECL 100K Compatible Parallel Data Interface;Differential High Speed Data Outputs ;Differential or Single-ended High Speed Data and Clock InDUtS;On-chip Phase Detector (VS8061 Multiplezer).

The VS8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates a divide-by-16 clock from the high speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended ECL compatible inputs (DO..D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.SGb/s serial output(DO/DON). The internal timing of the VS8061 is referenced to the negative going edge of the high speed clock true input (CLK). This clock is divided by 16 and is provided as an output (CLKI6/CLK16N). The setup and hold time of the parallel inputs (DO..D15) are specified with respect to the falling edge of CLK16, so that CLKI6/CLK16N can be used to clock the data source of DO..D15. The on-chip phase detector monitors the phase relationship between the internally generated divide by 16 clock and an externally supplied low speed reference clock input (DCLKIDCLKN). Phase difference between these two clock signals generates an up or down output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase Locked Loop (PLL) to implement a clock multiplication function.In applications where a 2.5 GHz system clock is provided, and the phase detector function is not required, it is recommended to connect one side of the DCLK/DCLKN input to V.}. through a 50 ohm resistor. The U and D output can be left open and unused.

Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differen-dally. Fgure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREP, for ECL levels be used for the complementary input.