VS8001

The VS8001 has the following features including Serial data: up to 1.25 Gb/s;ECL 100K/IOKH compatible parallel data inputs/outputs;Set input on VS8001 synchronizes external and internal clocks;Skip input on VS8002 for alignment of 12-bit output to word boundaries.

The VS8001 is a 12-bit parallel to serial data converter.  A fully synchronous internal design receives 12 parallel single-ended ECL bit streams(D0-D11)and converts these to a single differential bit stream (MUXDATA, NMUXDATA) up to 1.25 Gb/s.  To accommodate various system timing constraints, both the high frequency clock (CLK, NCLK) and low frequency divide by 12 clock(CLOCKI2) are driven off chip. A synchronizing input (SET) allows alignment of the internal low frequency clock to an externally supplied clock (DCLOCK). In addition to normal parallel to serial and serial to parallel data conversion hardware, the VS8001 and VS8002 contain features which allow the user to fully evaluate the at-speed functionality of the devices. Given some simple enabling signals(TEST, SYNCPATT), built in hardware causes the VS8001 to transmit multiplexed internally generated data patterns via its high speed serial port to the high speed serial input on the VS8002.  These signals allow the VS8002 to align itself to word boundaries and compare incoming data to its own internally generated, pseudo-random test patterns.Test enabling pins on the VS8002 consist of the TEST and SYNCPATT. Test is confirmed on the ALIGNED, ERRnR, FRAME and MATCH pins on the VS8002.

The pattern generator on the VS8001 creates twelve-bit patterns for the multiplexer, which then converts these twelve-bi( words into a serial data stream.  The serial output of the multiplexer is connected to the serial input of the demultiplexer. The demultiplexer converts this high speed serial data bit stream into twelve bit parallel data and compares the incoming data to patterns created by its own test pattern generator.The test hardware on the MUX consists of a 12-bit pattern generator with control logic.  The individual blocks are described below.