Features: `30/50MHz Pipeline Operation`Triple 8-Bit D-A Converters`±1 LSB Differential Linearity Error`±1 LSB Integral Linearity Error`Guaranteed Monotonic`RS-343A/RS-170 Compatible Levels`Drives Doubly Terminated 75 Load`Single 5V Power Supply`Typical Power Dissipation 500mW`Direct Replacement fo...
VP101: Features: `30/50MHz Pipeline Operation`Triple 8-Bit D-A Converters`±1 LSB Differential Linearity Error`±1 LSB Integral Linearity Error`Guaranteed Monotonic`RS-343A/RS-170 Compatible Levels`Drives Do...
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As shown in the Fig. 2, the VP101 contains three 8-bit D-A converters, input latches, and a loop amplifier.
On the rising edge of each VP101 clock cycle, (see Fig. 4), 24bits of colour information (R0-R7, G0-G7, and B0-B7) are latched into the device and presented to the three 8-bit D-A converters. The REF WHITE input, also latched on the rising edge of each clock cycle, and will force the inputs of each DA converter to $FF.
SYNC and BLANK are latched on the rising edge of the VP101 clock to maintain synchronisation with the colour data. These inputs add appropriately weighted currents to the analog outputs, producing the specific output levels required for video applications as shown in Fig. 3. Table 1 details how the SYNC, BLANK, and REFWHITE inputs modify the output levels.
The ISYNC current output is typically connected directly to the IOG output and is used to encode sync information onto the IOG output. If ISYNC is not connected to the IOG output, sync information will not be encoded on the green channel, and the IOR, IOG and IOB outputs will have the same full scale output current. Full Scale output current is set by an external resistor (RSET) between the FS ADJUST pin and AGND. RSET has a typical value of 542 for generation of RS-343A video into a 37.5 load. The VP101 may be used in applications where an external 1.2V (typical) reference is provided, in which case the external reference should be temperature compensated and provide a low impedance output. The D-A converters on the VP101 use a segmented architecture in which bit currents are routed to either the output or AGND by a sophisticated decoding scheme.This architecture eliminates the need for precision component ratios and greatly reduces the switching transients associated with turning current sources on or off.Monotonicity and low glitch energy are guaranteed by using identical current sources and current steering their outputs.An on-chip operational amplifier stabilises the full scale output current against temperature and power supply variations.
The analog outputs of the VP101 are capable of directly driving a 37.5 load, such as a doubly terminated 75coaxial cable or interpolation filters.