VM5711

The VM5711 has the following features including Compatible with Zoned-Density Recording Applications;Suitable for Many Applications in Data Communications Graphics, etc;Differential ECL Output Frequency from 40 to 200 MHz;Supports (1 ,7) Channel Data Rates up to 64 Mbits/sec;Compatible with VTC's VM5603, VM5355, and VM5351NM5352;User Determined PLL Loop Filter Network;Low Power Mode;Power Dissipation less than 500 mW typical;Power Supplies: +5 V Only.

The VM5711 is an integrated circuit designed to be used in high-performance zoned- density recording schemes. Its primary circuit function is to generate a variable frequency reference clock which is used as the fundamental system clock by the data recording channel. A serial microprocessor interface provides convenient access to internal registers which control the internal dividers and DAC. VM5711 can be used in zoned density schemes with recording frequency ratios of up to 1:2.5.Please consult VTC for package availability.The frequency synthesizer is implemented using a charge pump type Phase-Lock Loop (PLL) with programmable reference clock and VCO feedback frequency dividers. The frequency synthesizer consists of a VCO, charge pump, phase/frequency detector, and two programmable frequency dividers. Refer to the block diagram.The synthesizer reference clock signal that is used to drive the block comes into the chip through the CLKIN, CLKINN input pins. The Divide-by-N counter divides the incoming reference clock by a programmable integer value from 1 to 32. The output of the Divide-by-N becomes the reference clock for the synthesizer PLL. The Divide-by-M counter divides the CDCLK output by a programmable integer value from 1 to 256. The output of the Divide-by-M becomes the variable input to the synthesizer PLL. Both counters are programmed from the serial registers.

The phase/frequency detector block of VM5711 is a true frequency discriminating comparator with 2n radians per cycle usable for phase/frequency correction. An input pulse at the reference input initiates a pump-up signal to the Charge Pump and an input pulse at the variable input initiates a pump-down signal.When both pump-up and pump-down are true the circuit is reset. The minimum pump-up and pump-down pulse widths of VM5711 are determined by internal propagation delays and are about 5ns. In the locked condition, the pump-up and the pump-down signals are true for a short and equal period and are coincident in time. The pump-up and pump-down signals may be observed at the UP and DN test pins.