VM5701

The VM5701 has the following features including Designed for Zoned-Density Recording Operation with VTC's VM5601 and VM5355;Compatible wfth Other Applications, Including Data Communications, Graphics, etc;Crystal Oscillator or External TTL Reference Frequency Input;Differential ECL Output Frequency from 10 to 72 MHz;User Determined PLL Loop Filter Network;Power Dissipation Less Than 500 mW;Operates on a Power Supply of +5V;Available in a 20-Lead PLCC Package.

The VM5701 is an integrated circuit designed to be used in high-performance zoned density recording schemes with recording frequency ratios of up to 1:2.5. The VM5701 has three primary circuit functions:A reference clock generator that is used to synthesize the write/reference frequency used by the data recording channel.A current output DAC that is used to set the center frequency of the recording channel's data separator VC (e.g. VTC's VM5355).A crystal oscillator that can be used as the reference clock for the frequency synthesizer.Parallel registers hold the data to program the synthesizer frequency, an internal DAC and the data separator DAC. The parallel registers are loaded through a 13-bit serial register and a series-to-parallel conversion.The frequency synthesizer is implemented using a charge pump type Phase-Lock Loop (PLL) with programmable reference clock and VCO feedback frequency dividers. The frequency synthesizer consists of the VCO, the Charge Pump, and the Phase/Frequency Comparator, plus the two programmable dividers, Divide-by-M and Divide-by-N, as shown in the Block Diagram.

The Phase/Frequency Comparator block of VM5701 is a true frequency discriminating comparator with 21c radians per cycle usable for phase/frequency correction. An input pulse at the reference input initiates a pump-up signal to the Charge Pump and an input pulse at the variable input initiates a pump-down signal.When both pump-up and pump-down are true the circuit is reset. The minimum pump-up and pump-down pulse widths are determined by internal propagation delays and are about 5nsec. In the locked condition, the pump-up and the pump-down signals are true for a short and equal period and are coincident in time.