Features: · DSS and DVB-S compatible single chip demodulator & forward error correction.· Dual 6-bit ADC on chip.· PLL for crystal frequency multiplication.· Variable rate BPSK/QPSK coherent demodulator.· Modulation rate from 1 to 45MBaud.· Automatic Gain Control output.· Digital symbol timing...
VES1993: Features: · DSS and DVB-S compatible single chip demodulator & forward error correction.· Dual 6-bit ADC on chip.· PLL for crystal frequency multiplication.· Variable rate BPSK/QPSK coherent dem...
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Parameter |
Min | Max | Unit. |
Ambient operating temperature : Ta | 0 | 70 | |
DC supply voltageltage | -0.5 | + 4.1 | V |
DC Input voltage | -0.5 | VDD + 0.5 | V |
DC Input Current | ± 20 | mA | |
Lead Temperature | ±300 | ||
Junction Temperature | ±150 |
Stresses above the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
The VES1993 is a single-chip channel receiver for satellite television reception which matches both DSS and DVB-S standards. The VES1993 contains a dual 6-bit flash analog to digital converter, variable rate BPSK/QPSK coherent demodulator and Forward Error Correction functions.The ADCs directly interface with I and Q analog baseband signals. After A to D conversion, the VES 1993 implements a bank of cascadable filters as well as antialias and half-Nyquist filters. Analog AGC signal is generated by an amplitude estimation function. The VES1993 performs clock recovery at twice the Baud rate and achieves coherent demodulation without any feedback to the local oscillator. Forward Error Correction is built around two error correcting codes : a Reed-Solomon (outer code), and a Viterbi decoder (inner code). The Reed-Solomon decoder corrects up to 8 erroneous bytes among the N bytes of one data packet.Convolutional deinterleaver is located between the Viterbi output and the R.S. decoder input. De-interleaver and R.S. decoder are automatically synchronized thanks to the frame synchronisation algorithm which uses the sync pattern present in each packet. The VES 1993 is controlled via an I2C bus interface. The circuit operates up to 91MHz and can process variable modulation rates, up to 45Mbaud.
The VES1993 provides an interrupt line which can be programmed on either events or timing information.Designed in 0.35 CMOS technology and housed in a 100-MQFP package, the VES 1993 operates over the commercial temperature range.