Features: High-speed: 10, 12, 15 ns Fully static operation All inputs and outputs directly TTL compatible Three state outputsLow data retention current (VCC = 2V) Single 5V ± 10% Power SupplyLow CMOS Standby current of 5 mA maxPackages 32-pin TSOP 32-pin 300 mil SOJPinoutSpecifications Sy...
V61C5181024: Features: High-speed: 10, 12, 15 ns Fully static operation All inputs and outputs directly TTL compatible Three state outputsLow data retention current (VCC = 2V) Single 5V ± 10% Power SupplyLow CMO...
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Features: High-speed: 10, 12, 15 ns All inputs and outputs directly TTL compatible Three state out...
Features: High-speed: 10, 12, 15 ns Fully static operation All inputs and outputs directly TTL c...
Features: High-speed: 10, 12, 15 nsAll inputs and outputs directly TTL compatibleThree state outp...
Symbol |
Parameter |
Commercial |
Units |
VCC |
Supply Voltage |
-0.5 to +7 |
V |
VN |
Input Voltage |
-0.5 to +7 |
V |
VDQ |
Input/Output Voltage Applied |
VCC + 0.5 |
V |
TBIAS |
Temperature Under Bias |
-10 to +125 |
°C |
TSTG |
Storage Temperature |
65 to +150 |
°C |
The V61C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The V61C5181024 is available in 32-pin SOJ, PDIP and TSOP.