Features: *25ns maximum (3.3 volt supply) address access time* MCM contains four (4) 512K x 8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24, or 32-bit data width* TTL compatible inputs and output levels, three-state bidirectional data bus* Typical rad...
UT8Q512K32: Features: *25ns maximum (3.3 volt supply) address access time* MCM contains four (4) 512K x 8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24, or 32-bit ...
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Features: 25ns maximum (3.3 volt supply) address access time Dual cavity package contains two (2) ...
SYMBOL | PARAMETER | LIMITS |
VDD | DC supply voltage | -0.5 to 4.6V |
VI/O | Voltage on any pin | -0.5 to 4.6V |
TSTG | Storage temperature | -65 to +150 |
PD | Maximum power dissipation | 1.0W (per byte) |
TJ | Maximum junction temperature2 | +150 |
QJC | Thermal resistance, junction-to-case3 | 10°C/W |
II | DC input current | ±10 mA |
Each die in the UT8Q512K32 has three control inputs called Enable (En), Write Enable (Wn), and Output Enable (G); 19 address inputs, A(18:0); and eight bidirectional data lines, DQ(7:0). The UT8Q512K32 enable (En) controls device selection, active, and standby modes. Asserting En enables the device, causes IDD to rise to its active value, and decodes the 19 address inputs to each memory die by selecting the 2,048,000 byte of memory. Wn controls read and write operations. During a read cycle, G must be asserted to enable the outputs.