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USB97C100

Features: · High Performance USB Peripheral Controller Engine- Integrated USB Transceiver- Serial Interface Engine (SIE)- 8051 Microcontroller (MCU)- Patented Memory Management Unit (MMU)- 4 Channel 8237 DMA Controller (ISADMA)- 4K Byte On Board USB Packet Buffer- Quasi-ISA Peripheral Interface- ...

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SeekIC No. : 004538815 Detail

USB97C100: Features: · High Performance USB Peripheral Controller Engine- Integrated USB Transceiver- Serial Interface Engine (SIE)- 8051 Microcontroller (MCU)- Patented Memory Management Unit (MMU)- 4 Channe...

USB97C100 Data Sheet

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Part Number:
USB97C100
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/22

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Product Details

Description



Features:

· High Performance USB Peripheral Controller Engine
- Integrated USB Transceiver
- Serial Interface Engine (SIE)
- 8051 Microcontroller (MCU)
- Patented Memory Management Unit (MMU)
- 4 Channel 8237 DMA Controller (ISADMA)
- 4K Byte On Board USB Packet Buffer
- Quasi-ISA Peripheral Interface
- USB Bus Snooping Capabilities
- GPIOs
· Complete USB Specification 1.1 Compatibility
- Isochronous, Bulk, Interrupt, and Control
  Data Independently Configurable per Endpoint
- Dynamic Hardware Allocation of -Packet
  Buffer for Virtual Endpoints
- Multiple Virtual Endpoints (up to 16 TX, 16
  RX Simultaneously)
- Multiple Alternate Address Filters
- Dynamic Endpoint Buffer Length
  Allocation (0-1280 Byte Packets)
· High Speed (12Mbps) Capability
· MMU and SRAM Buffer Allow Buffer Optimization
  and Maximum Utilization of USB Bandwidth
- 128 Byte Page Size
- 10 Pages Maximum per Packet
- Up to 16 Deep Receive Packet Queue
- Up to 5 Deep Transmit Packet Queue, per Endpoint
- Hardware Generated Packet Header
  Records Each Packet Status Automatically
- Simultaneous Arbitration Between MCU,
  SIE, and ISA DMA Accesses
· Extended Power Management
- Standard 8051 "Stop Clock" Modes
- Additional USB and ISA Suspend
  Resume Events
- Internal 8MHz Ring Oscillator for Immediate
  Low Power Code Execution
- 24, 16, 12, 8, 4, and 2 MHz PLL Taps For on
  the Fly MCU and DMA Clock Switching
- Independent Clock/Power Management for
  SIE, MMU, DMA and MCU
· DMA Capability with ISA Memory
- Four Independent Channels
- Transfer Between Internal and External Memory
- Transfer Between I/O and Buffer Memory
- External Bus Master Capable
· External MCU Memory Interface
- 1M Byte Code and Data Storage via 16K Windows
- Flash, SRAM, or EPROM
- Downloadable via USB, Serial Port, or ISA Peripheral
· Quasi-ISA Interface Allows Interface to New and
"Legacy" Peripheral Devices
- 1M ISA Memory Space via 4K MCU Window
- 64K ISA I/O Space via 256 Byte MCU Window
- 4 External Interrupt Inputs
- 4 DMA Channels
- Variable Cycle Timing
- 8 Bit Data Path
· 5V or 3.3v Operation
· On Board Crystal Driver Circuit
· 128 Pin QFP Package


Pinout

Connection Diagram


Specifications

Operating Temperature Range........................................................................................................................0oC to +70oC
Storage Temperature Range ........................................................................................................................-55o to +150oC
Lead Temperature Range (soldering, 10 seconds).....................................................................................................+325oC
Positive Voltage on any pin, with respect to Ground................................................................................................Vcc+0.3V
Negative Voltage on any pin, with respect to Ground ....................................................................................................-0.3V
Maximum Vcc ................................................................................................................................................................... +7V
*Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only
and functional operation of the device at any other condition above those indicated in the operation sections of this
specification is not implied.
Note: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when
the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output.
When this possibility exists, it is suggested that a clamp circuit be used.


Description

The USB97C100 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple endpoint applications. The USB97C100 provides an ISA-like bus interface, which will allow virtually any PC peripheral to be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection's overall bandwidth. This architecture minimizes the integrated microcontroller's participation in the USB data flow, allowing backto- back packet transfers to block oriented devices. The efficiency of this architecture of the USB97C100 allows floppy drives to coexist with other peripherals such as serial and parallel ports on a single USB link.

The USB97C100 allows external program code to be downloaded over the USB to allow easy implementation of varied peripheral USB Device Classes and combinations. This also provides a method for convenient field upgrades and modifications.




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