Features: ` Available in a 40 ball lead-free RoHS compliant (4 x 4 x 0.9mm) VFBGA package` Interface compliant with the UTMI specification (60MHz, 8-bit bidirectional interface)` Only one required power supply (+3.3V)` Supports 480Mbps Hi-Speed (HS) and 12Mb...
USB3290: Features: ` Available in a 40 ball lead-free RoHS compliant (4 x 4 x 0.9mm) VFBGA package` Interface compliant with the UTMI specification (60MHz, 8-bit bidirectional interface)&...
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The USB3290 is the ideal companion to any ASIC, SoC or FPGA solution designed with a UTMI Hi-Speed USB device (peripheral) core.
The USB3290 is well suited for:
· Cell Phones
· MP3 Players
· Scanners
· External Hard Drives
· Digital Still and Video Cameras
· Portable Media Players
· Entertainment Devices
· Printers
PARAMETER | SYMBOL | CONDITIONS | MIN | TYP | MAX | UNITS |
Maximum DP and DM voltage to Ground |
VMAX_5V | -0.3 | 5.5 | V | ||
Maximum VDD1.8 and VDDA1.8 voltage to Ground |
VMAX_1.8V | -0.3 | 2.5 | V | ||
Maximum 3.3V Supply Voltage to Ground |
VMAX_3.3V | -0.3 | 4.0 | V | ||
Maximum I/O Voltage to Ground |
VI | -0.3 | 4.0 | V | ||
Storage Temperature | TSTG | -55 | 150 | |||
ESD PERFORMANCE | ||||||
All Pins | VHBM | Human Body Model | ±5 | kV | ||
LATCH-UP PERFORMANCE | ||||||
All Pins | ILTCH_UP | EIA/JESD 78, Class II | 150 | mA |
The USB3290 is an industrial temperature USB 2.0 physical layer transceiver (PHY) integrated circuit. SMSC's proprietary technology results in low power dissipation, which is ideal for building a bus powered USB 2.0 peripheral. The PHY uses an 8-bit bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps.
All required termination and 5.25V short circuit protection of the DP/DM lines are internal to the chip. The USB3290 also has an integrated 1.8V regulator so that only a 3.3V supply is required.
While transmitting data of the USB3290, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding.