Features: On-chip clock recovery/clock synthesis functionsProvides TC sub-layer function for the ATM protocol's physical layerSupported frame formats include 155 Mbps SONET STS-3c/SDH STM-1Conforms to ATM Forum UTOPIA interface Level 2 V1.0 (af-phy-0039.000 June 1995)Supports three UTOPIA interfac...
UPD98404: Features: On-chip clock recovery/clock synthesis functionsProvides TC sub-layer function for the ATM protocol's physical layerSupported frame formats include 155 Mbps SONET STS-3c/SDH STM-1Conforms ...
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Item | Symbol | Condition | Ratings | Unit |
Power supply voltage | VDD | 0.5 to +4.6 | V | |
Input/output voltage | VI1/VO1 | Pin other than P-ECL, analog level | 0.5 to +6.6 or VDD +3.0 | V |
VI2/VO2 | P-ECL, analog level | 0.5 to +4.6 or VDD +0.5 | V | |
Operating temperature | TA | 45 to +85 | °C | |
Storage temperature | Tstg | 65 to +150 | °C |
The PD98404 NEASCOT-P30TMis an LSI for ATM applications, which can be used in ATM adapter boards for connecting PCs or workstations to an ATM network and can also be used in ATM hubs and ATM switches. This LSI provides the TC sub-layer functions in the SONET/SDH-base physical layer within the ATM protocol defined by the ATM Forum's UNI3.1 recommendations.
This PD98404 NEASCOT-P30TM product's main functions include transmission functions such as mapping of ATM cells sent from the ATM ayer to the payload field in a 155 Mbps SONET STS-3c/SDH STM-1 frame and transmission to PMD (Physical Media Dependent) sub-layer in the physical layer. Its reception functions include separation of the overhead from the ATM cells in data streams received from PMD sub-layer and transmission of the ATM cells to the ATM layer. In addition, this LSI includes a clock recovery function that extracts a reception sync clock from bit streams in received data and a clock synthesis function that generates a clock for transmissions.