UCC561DPTRG4

(1) Stresses beyond those listed under "absolutemaximumratings"may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended  perating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Currents are positive into and negative out of the specified terminals.

The UCC561 low-voltage differential (LVD) regulator set is designed to provide the correct references voltages and bias currents for LVD termination resistor networks (475
, 121
, and 475
). The devic o  provides a 1.3-V output for "diff sense" signaling. With the proper resistor network, theUCC561 solutionmeets the common mode bias impedance, differential bias, and termination impedance requirements of SPI--2 (Ultra2), SPI--3 (Ultra3/Ultra160) and SPI--4 (Ultra320). The UCC561 is not intended for SPI--5 applications. This device incorporates into a single monolith, two sink/source reference voltage regulators, a 1.3-V buffered output and protection features. The protection features include thermal shutdown and active current-limiting circuitry. The UCC561 is offered in 16-pin SOIC (DP) package.