Features: • High-performance CMOS nonvolatilestatic RAM 32768 x 8 bits• 25, 35 and 45 ns Access Times• 10, 15 and 20 ns Output EnableAccess Times• ICC = 15 mA typ. at 200 ns CycleTime• Automatic STORE to EEPROMon Power Down using externalcapacitor• Hardware or S...
U634H256XS: Features: • High-performance CMOS nonvolatilestatic RAM 32768 x 8 bits• 25, 35 and 45 ns Access Times• 10, 15 and 20 ns Output EnableAccess Times• ICC = 15 mA typ. at 200 ns ...
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Absolute Maximum Ratings | Symbol | Min. | Max. | Unit |
Power Supply Voltage | VCC | -0.5 | 7 | V |
Input Voltage | VI | -0.3 | VCC+0.5 | V |
Output Voltage | VO | -0.3 | VCC+0.5 | |
Power dissipation | PD | 1 | W | |
Operating Temperature C-Type K-Type |
Ta | 0 -40 |
70 85 |
|
Storage Temperature | Tstg | -65 | 150 |
The U634H256XS has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM.
In this mode SRAM functions are disabled. The U634H256XS is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM U634H256XS can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 F capacitor.
Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up. The U634H256XS combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles U634H256XS also may be initiated under user control via a software sequence or via a single pad (HSB). Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed.
Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles of U634H256XS may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells.
The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data of U634H256XS can be recalled an unlimited number of times. The chips are tested with a restricted wafer probe program at room temperature only. Untested parameters are marked with a number sign (#).