U634H256

` High-performance CMOS nonvolatile static RAM 32768 x 8 bits
` 25, 35 and 45 ns Access Times
` 10, 15 and 20 ns Output Enable Access Times
` I_CC = 15 mA typ. at 200 ns Cycle Time
` Automatic STORE to EEPROM on Power Down using external capacitor
` Hardware or Software initiated STORE
                                   (STORE Cycle Time < 10 ms)
` Automatic STORE Timing
` 10⁵ STORE cycles to EEPROM
` 10 years data retention in EEPROM
` Automatic RECALL on Power Up
` Software RECALL Initiation (RECALL Cycle Time < 20 s)
` Unlimited RECALL cycles from EEPROM
` Single 5 V ± 10 % Operation
` Operating temperature ranges:
                                    0 to 70 °C
                                 -40 to 85 °C
                             -40/-55 to 125 °C (only 35 ns)
` QS 9000 Quality Standard
` ESD protection > 2000 V (MIL STD 883C M3015.7-HBM)
` Packages: SOP32 (300 mil),PDIP32 (600 mil, only C/K-Type)

a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The U634H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled.

The U634H256 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an  unlimited number of times, while independent nonvolatile data resides in EEPROM. Data of U634H256 transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in an external 100 µF capacitor.

Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on power up.

The U634H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity.STORE cycles also may be initiated under user control via a software sequence or via a single pin (HSB).

Once a STORE cycle is initiated,further input or output are disabled until the cycle is completed.Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted.

RECALL U634H256 cycles may also be initiated by a software sequence.

Internally, RECALL U634H256 is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells.

The RECALL U634H256 operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.