U62H64

· Fast 8192 x 8 bit static CMOS  RAM
· 35 ns Access Time
· Bidirectional data inputs and data outputs
· Three-state outputs
· Data retention mode at Vcc > 2V
· Data retention current at 2 V:< 3 µA (K-Type) < 50 µA (A-Type)
· Standby current < 5 µA (K-Type) < 100 µA (A-Type)
· TTL/CMOS-compatible
· Automatic reduction of power dissipation in long Read or Write cycles
· Power supply voltage 5 V
· Operating temperature ranges
                               -40 to 85 °C
                             -40 to 125 °C
· QS 9000 Quality Standard
· ESD protection > 2000 V (MIL STD 883C M3015.7)
· Latch-up immunity > 200 mA
· Package: SOP28 (300 mil)

a Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect reliability

b Maximum voltage is 7 V

c Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

The U62H64 is a static RAM manufactured using a CMOS process technology with the following operating modes:
         - Read          - Standby
         - Write          - Data Retention
The memory array is based on a 6-transistor cell.

The circuit of U62H64 is activated by the rising edge of E2 (at E1 = L), or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously.

According to the information of W and G, the data inputs, or outputs,are active. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address change, the data outputs go High-Z until the new read information is available. The data outputs of U62H64 have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at I_O = 0 mA) drops to the value of the operating
current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively.

Data retention of U62H64 is guaranteed down to 2 V.With the exception of E1 and E2,all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit of U62H64 allows to achieve low power standby requirements by activation with TTL-levels too.