Features: • Smallest possible lock-in time; no asynchronous divider stage• 1-chip system for MPU control (I2C Bus)• Fast I2C Bus mode possible• 4 programmable chip addresses• Short pull-in time for quick channel switch-over and optimized loop stability• 3 high-c...
TUA6010X: Features: • Smallest possible lock-in time; no asynchronous divider stage• 1-chip system for MPU control (I2C Bus)• Fast I2C Bus mode possible• 4 programmable chip addresses&...
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Parameter | Symbol | Limit Values | Unit | Notes | |
min. | max. | ||||
PLL | |||||
Supply voltage | IVCCD | 0.3 | 6 | V | - |
Current | IVCCD | 38 | mA | ||
Output CHGPMP | VCHGPMP | 0.3 | 3.5 | V | |
Crystall oscillator pins Q, Q | VQ | 0.3 | VVCCD | V | |
Bus input/output SDA | VSDA | 0.3 | 6 | V | |
Bus input SCL | VSCL | 0.3 | 6 | V | |
Port outputs P0, P1, P2 | VP | 0.3 | 13 | V | |
Chip address switch CAS | VCAS | 0.3 | VVCCD | V | |
Output active filter TUNE | VTUNE | 0.3 | 33 | V | |
Bus output SDA | ISDAL | 1 | 5 | mA | Open collector |
Port outputs P0, P1, P2 | IPL | 1 | 15 | mA | Open collector |
Total port output current | S IPL | 20 | mA | ||
Junction temperature | TJ | 125 | °C | - | |
Storage temperature | TS | 40 | 125 | °C | |
Thermal resistance (junction to ambient) |
RthA | 75 | K/W | ||
Mixer Oscillator | |||||
Supply voltage | IVCCA | 0.3 | 6 | V | |
Current | IVCCA | 38 | mA | ||
Output IF, IF | IIF, IF | 9 | mA | Open collector |
The TUA6010X device combines a digitally programmable phase locked loop (PLL), with a mixer oscillator block including two balanced mixers and oscillators for use in TV tuners.
The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 1.1 GHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The device has three output ports, which all can also be used as input ports (two TTL inputs and one A/D converter input). A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C Bus.
The mixer oscillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and a band switch.