TSPC603R

The TSPC603R implementation of PowerPC603e (after named 603r) is a low-power implementation of reduced instruction set computer (RISC) microprocessors PowerPC  family. The 603r implements 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.

The TSPC603R is a low-power 2.5/3.3-volt design and provides four software controllable power-saving modes. The 603r is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the 603r makes completion appear sequential.

The TSPC603R integrates five execution units and is able to execute five instructions in parallel. The 603r provides independent on-chip, 16K byte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look aside buffers that provide support for demand-paged virtual memory address translation and variable-sized block translation.

The TSPC603R has a selectable 32 or 64-bit data bus and a 32-bit address bus. The 603r interface protocol allows multiple masters to complete for system resources through a central external arbiter. The 603r supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O.