TSPC106

Features:

•Processor Bus Frequency Up to 66 MHz and 83.3 MHz
•64-bit Data Bus and 32-bit Address Bus
•L2 Cache Control for 256-Kbyte, 512-Kbyte, 1-Mbyte Sizes
•Provides Support for Either Asynchronous SRAM, Burst SRAM or Pipelined Burst SRAM
•Compliant with PCI Specification, Revision 2.1
•PCI Interface Operates at 20 to 33 MHz, 3.3V/5.0V-compatible
•IEEE 1149.1-compliant, JTAG Boundary-scan Interface
•PD Max = 1.7 Watts (66 MHz), Full Operating Conditions
•Nap, Doze and Sleep Modes Reduce Power Consumption
•Fully Compliant with MIL-STD-883 Class Q or According to Atmel Standards
•Upscreenings Based on Atmel Standards
•Full Military Temperature Range (-55°C T_j +125°C)
   Industrial Temperature Range (-40°C T_j +110°C)
•V_CC = 3.3V ± 5%
•Available in a 303-ball CBGA or a 303-ball CBGA with Solder Column Interposer (SCI) (CI-CGA) Package


Specifications

Symbol	Parameter	Min	Max	Unit
VDD	Supply Voltage	-0.3	3.6	V
AVDD	PLL Supply Voltage	-0.3	3.6	V
VIN	Input Voltage	-0.3	5.5	V
TSTG	Storage Temperature Range	-55	+150	°C

Notes:
1.Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device.
2.Caution: Input voltage must not be greater than the VDD supply voltage by more than 2.5V at all times including during power-on reset.


Description

The TSPC106 provides an integrated, high-bandwidth, high-performance, TTL-compatible interface between a 60x processor, a secondary (L2) cache or up to a total of four additional 60x processors, the PCI bus and main memory.

PCI support allows system designers to rapidly design systems using peripherals already designed for PCI.

The TSPC106 uses an advanced 3.3V CMOS-process technology and maintains full interface compatibility with TTL devices.

The TSPC106 integrates system testability and debugging features via JTAG boundary-scan capability.