TSM1N60S

Features: 􀂗· Robust high voltage termination􀂗· Avalanche energy specified􀂗· Diode is characterized for use in bridge circuits􀂗· Source to Drain diode recovery time comparable to a discrete fast recovery diode.􀂗· IDSS and VDS(on) specified at elevated te...

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SeekIC No. : 004529634 Detail

TSM1N60S: Features: 􀂗· Robust high voltage termination􀂗· Avalanche energy specified􀂗· Diode is characterized for use in bridge circuits􀂗· Source to Drain diode recovery tim...

floor Price/Ceiling Price

Part Number:
TSM1N60S
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

􀂗· Robust high voltage termination
􀂗· Avalanche energy specified
􀂗· Diode is characterized for use in bridge circuits
􀂗· Source to Drain diode recovery time comparable to a discrete fast recovery diode.
􀂗· IDSS and VDS(on) specified at elevated temperature



Specifications

Parameter Symbol Limit Unit
Drain-Source Voltage VDS 600V V
Gate-Source Voltage VGS ± 30 V
Continuous Drain Current ID 0.3 A
Pulsed Drain Current IDM 1.2 A
Maximum Power Dissipation Ta = 25 °C PD 3 W
Ta > 25 °C 0.025 W/°C
Operating Junction Temperature TJ +150 °C
Operating Junction and Storage Temperature Range TJ, TSTG - 55 to +150 °C
Single Pulse Drain to Source Avalanche Energy
(VDD = 50V, VGS=10V, IAS=0.3A, L=115mH)
EAS 50 mJ



Description

The TSM1N60S is used an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. In addition, this advanced MOSFET is designed to withstand high energy in  valanche and commutation modes. The new energy efficient design also offers a drain- to-source diode with a fast recovery time.Designed for high voltage, high speed switching applications in power supplies and converters, the TSM1N60S is particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional and safety margin against unexpected voltage transients




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