TSC80251G1D

Features:

PinOut and software compatibility with standard 80C51 products and 80C51FA/FB/RA/RB
Plugin replacement of Intel's 80C251Sx
C251 core: Intel's MCS^®251 step D compliance
  83 ns Instruction cycle time @ 24 MHz
  40byte Register File
  Registers Accessible as Bytes, Words or Dwords
  Sixstage Instruction Pipeline
  16bit Internal Code Fetch
Enriched C51 Instruction Set
  16bit and 32bit ALU
  Compare and Conditional Jump Instructions
  Expanded Set of Move Instructions
Linear Addressing
1 Kbyte of onchip RAM
External memory space (Code/Data) programmable from 64 Kbytes to 256 Kbytes
TSC83251G1D: 16 Kbytes of onchip masked ROM (Engineering and fast production with TSC87251G1A OTP/EPROM version)
TSC80251G1D: ROMless version
Four 8bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the standard 80C51)
Serial I/O Port: full duplex UART (80C51 compatible) with independent Baud Rate Generator
SSLC: Synchronous Serial Link Controller
  I2C multimaster and slave protocols
  mWire and SPI master and slave protocols
Three 16bit Timers/Counters (Timers 0, 1 and 2 of the standard 80C51)
EWC: Event and Waveform Controller
  Compatible with Intel's Programmable Counter Array (PCA)
  Common 16bit Timer/Counter reference with four possible clock sources (Fosc/4, Fosc/12, Timer 1 and external input)
  Five modules with four programmable modes:
    16bit software Timer/Counter
    16bit Timer/Counter Capture Input and software pulse measurement
    Highspeed output and 16bit software Pulse Width Modulation (PWM)
    8bit hardware PWM without overhead
  16bit Watchdog Timer/Counter capability
Secure 14bit Hardware Watchdog Timer
Power Monitoring and Management
  PowerFail reset
  PowerOn reset (integrated on the chip)
  PowerOff flag (cold and warm resets)
  Software programmable system clock
  Idle and PowerDown modes
Keyboard interrupt interface on Port 1
Non Maskable Interrupt input (NMI)
Realtime Wait states inputs (WAIT#/AWAIT#)
Onchip Code Verify with Encryption for Mask ROM versions
ONCE mode and full speed RealTime InCircuit Emulation support (Third Party Vendors)
High speed versions:
  16 MHz and 24 MHz
  5 V ±10 %
  Typical operating current: 34 mA @ 24 MHz     23 mA @ 16 MHz
  PowerDown mode typical current2 A
Low voltage version:
  2.7 V to 5.5 V
  12 MHz operation
  Typical operating current: 8 mA @ 3 V
  PowerDown mode typical current 1 A
Temperature ranges:
  Commercial (0°C to +70°C)
  Industrial (40°C to +85°C)
Option: extended range (55°C to +125°C)
Packages:
  PDIL 40, PLCC 44 and VQFP 44
  Options: known good dice and ceramic packages


Application

ISDN terminals
HighSpeed modems
PABX (SOHO)
Networking
Line cards
Computer peripherals
Printers
Plotters
Scanners
Banking machines
Barcode readers
Smart cards readers
Highend digital monitors
Highend joysticks


Pinout




Specifications

Storage Temperature . . . . . . . . . . . . . . . . . . . .65 to +150°C
Voltage on any other Pin to VSS  . . . . . . . . . . .0.5 to +6.5 V
I_OL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . .15 mA
Power Dissipation  . . . . . . . . . . . . . . . . . . . . . .1.5 W






Description

The TSC80251G1D products are derivatives of the TEMIC Microcontroller family based on the extended 8bit C251 Architecture. This family of products is tailored to 8bit microcontroller applications requiring an increased instruction throughput, a reduced operating frequency or a larger addressable memory space. The architecture can provide a significant code size reduction when compiling C programs while fully preserving the legacy of C51 assembly routines.

The TSC80251G1D derivatives are pinout and software compatible with standard 80C51/Fx/Rx with extended onchip data memory (1 Kbyte RAM) and up to 256 Kbytes of external code and data. Additionally, the TSC83251G1D provides onchip code memory (16 Kbytes ROM).

They provide transparent enhancements to Intel's 8xC251Sx family with an additional Synchronous Serial Link Controller (SSLC supporting I²C, mWire and SPI protocols), a Keyboard interrupt interface and Power Monitoring and Management features.

TSC80251G1D Mask ROM and ROMless derivatives are optimized both for speed and for low power consumption on a wide voltage range.

Notes:
This Datasheet provides the technical description of the TSC80251G1D derivatives. For further information on the device usage, please request the TSC80251 Programmers' Guide and the TSC80251G1D Design Guide.

For information on the EPROM/OTP devices, please refer to the TSC87251G1A Datasheet.