Features: • Integer Unit Based on SPARC V7 High-performance RISC Architecture• Optimized Integrated 32/64-bit Floating-point Unit• On-chip Peripherals EDAC and Parity Generator and Checker Memory Interface Chip Select Generator Waitstate Generation Memory Protection DMA Arbite...
TSC695F: Features: • Integer Unit Based on SPARC V7 High-performance RISC Architecture• Optimized Integrated 32/64-bit Floating-point Unit• On-chip Peripherals EDAC and Parity Generator an...
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Military Range............................................ -55°C to +125°C
Storage Temperature ................................ -65°C to +150°C
Supply Voltage...................................................-0.5V to +7.0V
Input Voltage.....................................................-0.5V to +7.0V
Note: Stresses at or above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications.
The processor of TSC695F is manufactured using the Atmel 0.5 m radiation tolerant ( 300 KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection.
The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers a high security watchdog, two timers, an interrupt controller, parallel and serial interfaces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), and a boundary scan through JTAG interface.