TSC692E

Specifications

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 ° C to +150 ° C
Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 ° C to +125 ° C
Supply Voltage^[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +7.0 V


Description

Figure 1. illustrates the functional block diagram for the TSC692E. The fetch unit captures instructions and their addresses from the D[31:0] and A[31:0] busses. The decode unit contains  logic to decode the floatingpoint instruction opcodes. The execution unit handles all instruction execution. The execution unit includes a floatingpoint queue (FP queue), which contains stored floatingpoint operate (FPop) instructions (see Section 3.3.2) under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit.

The load unit holds data that is fetched from memory via the data bus before it is written into the register file. The register file contains the 32 f registers. The exceptions/floatingpoint status register (FSR) unit keeps the status of completing FPops, as well as the operating mode of the TSC692E. The store unit holds data that is supplied to the data bus during a store operation. The dependency checking unit checks for conditions where the FPU must freeze the TSC691E integer unit pipeline so that an incoming instruction does not overflow the floatingpoint queue. The datapath unit contains arithmetic logic used by FPops to operate on the data in the register file and is comprised of a Fractional, Exponent and Sign units. Figure 2. gives a more detailed block diagram of the TSC692E.

The TSC692E provides three types of registers: f registers, FSR, and the FP queue. The f registers are the thirtytwo floatingpoint operand registers, each 32bits in size. Adjacent evenodd f register pairs (for instance, f0 and f1 can be concatenated to support doubleprecision operands). The FSR is a 32bit status and control register. It keeps track of rounding modes, floatingpoint trap types, queue status, condition codes, and various IEEE exception information.

The floatingpoint queue contains the floatingpoint instruction currently under execution, along with its corresponding address. The floatingpoint queue provides an efficient method of handling floatingpoint exceptions. When an FPop instruction causes a floatingpoint exception, the queue contains the offending instruction/address pair along. The TSC691E integer unit acknowledges the floatingpoint exception, enters a floatingpoint trap routine, empties the queue, and corrects the exception case. After the exception case is corrected, unfinished floatingpoint instruction found in the floatingpoint queue is either executed or emulated in the trap handler before returning to normal execution.

The TSC692E depends upon the TSC691E to assert all addresses and control signals for memory access. Floatingpoint loads and stores are executed in conjunction with the TSC691E, which provides addresses and control signals while the TSC692E supplies or stores the data. Instruction fetch for integer and floatingpoint instructions is provided by the TSC691E. When the TSC691E integer unit asserts an address for an instruction fetch, it asserts the INST signal one clock later. The TSC692E floatingpoint unit uses INST to determine when a valid instruction is present on the D[31:0] bus. The instruction, which appears on the data bus on the next clock cycle, is latched and paired with its corresponding address. In any given cycle, one instruction/address pair is stored by the TSC692E, regardless of whether the instruction is an integer or floatingpoint instruction. This instruction/address pair may be selected for execution by the TSC691E upon asserting the FINS1 or FINS2 signal. The FINS1 or FINS2 signals enables a floatingpoint instruction to begin execution by the TSC692E.

Upon decoding a floatingpoint instruction, the TSC691E will assert the FINS1 or the FINS2 signal to enable the TSC692E to begin execution. The FINS1 or FINS2 signal is asserted during the decode stage of the floatingpoint instruction, and is recognized by the TSC692E at the beginning of the execute stage of the floatingpoint instruction. This ensures synchronization of the decode and execute stages of a floatingpoint instruction between instruction pipelines of the TSC691E and the TSC692E.