TSB83AA22C

` Fully Supports Provisions of IEEE Std 1394b-2002 Revision 1.33+ at 1-Gigabit Signaling Rates
` Fully Supports Provisions of IEEE Std 1394a-2000 and IEEE Std 1394-1995 Standards for High-Performance Serial Bus
` Fully Interoperable With Firewire™, i.LINK™ and SB1394 Implementations of IEEE Std 1394
` Provides Two Fully Backward-Compatible, IEEE Std 1394a-2000 Fully Compliant) Bilingual IEEE Std 1394b-2002 Cable Ports at up to 800 Megabits per Second (Mbps)
` Full IEEE Std 1394a-2000 Support Includes:
Connection Debounce
Arbitrated Short Reset
Multispeed Concatenation
Arbitration Acceleration
Fly-By Concatenation
Port Disable/Suspend/Resume
` Extended Resume Signaling for Compatibility With Legacy DV Devices
` Power-Down Features to Conserve Energy in Battery-Powered Applications
` Low-Power Sleep Mode
` Fully Compliant With Open Host Controller Interface (OHCI) Requirements
` Cable Power Presence Monitoring
` Cable Ports Monitor Line Conditions for Active Connection to Remote Node
` Register Bits Give Software Control of Contender Bit, Power-Class Bits, Link Active Control Bit, and IEEE Std 1394a-2000 Features
` Interoperable With Other 1394 Physical Layers (Phy) Using 1.8-V, 3.3-V, and 5-V Supplies
` Low-Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbps and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz
` Separate Bias (TPBIAS) for Each Port
` Software Device Reset (SWR)
` Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports Ensure That the TSB83AA22C Does Not Load the TPBIAS of Any Connected Device and Blocks any Leakage From the Port Back to Power Plane
` IEEE Std 1394a-2000-Compliant Common-Mode Noise Filter on Incoming Bias Detect Circuit to Filter Out Crosstalk Noise
` Port Programmable to Force IEEE Std 1394a-2000 Mode to Allow Use of IEEE Std 1394a-2000 Connectors (IEEE Std 1394b-2002 Signaling Must Not Be Put Across IEEE Std 1394a-2000 Connectors or Cables)
` 3.3-V and 5-V PCI Signaling Environments
` Serial-Bus Data Rates of 100 Mbps, 200 Mbps, 400 Mbps, and 800 Mbps
` Physical Write Posting of up to Three Outstanding Transactions
` Serial ROM or Boot ROM Interface Supports 2-Wire Serial EEPROM Devices
` 33-MHz/32-Bit PCI Interface
` Multifunction Terminal (MFUNC Terminal 1):
PCI_CLKRUN Protocol per the PCI Mobile Design Guide
General-Purpose I/O
CYCLEIN/CYCLEOUT for External Cycle Timer Control for Customized Synchronization
` PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency:
Transmit FIFO-5K Asynchronous
Transmit FIFO-2K Isochronous
Receive FIFO-2K Asynchronous
Receive FIFO-2K Isochronous
` D0, D1, D2, and D3 Power States and PME Events per the PCI Bus Power Management Interface Specification
` Programmable Asynchronous Transmit

The TSB83AA22C is an IEEE Std 1394b-2002 link-layer design and Phy design combined in a single package to meet the demanding requirements of today's 1394 bus applications. The TSB83AA22C device is capable of exceptional 800-Mbps performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses. The TSB83AA22C device also provides outstanding ultralow-power operation and intelligent power management capabilities. The device provides the IEEE 1394 LLC function and Phy function and is compatible with 100 Mbps, 200 Mbps, 400 Mbps, and 800 Mbps serial-bus data rates.

The TSB83AA22C operates as the interface between 33-MHz/32-bit PCI local bus and an IEEE Std 1394a-2000 or IEEE Std 1394b-2002 serial bus interface. It is capable of supporting serial data rates at 98.304, 196.608, 393.216, 491.52, or 786.432 Mbps (referred to as S100, S200, S400, S400B, or S800 speeds, respectively). When acting as a PCI bus master, the TSB83AA22C device is capable of multiple cacheline bursts of data, which can transfer at 132M bytes/s for 32-bit transfers after connecting to the memory controller. Due to the high throughput potential of the TSB83AA22C device, it possible to encounter large PCI and legacy 1394 bus latencies, which can cause the 1394 data to be overrun. To overcome this potential problem, the TSB83AA22C implements deep transmit and receive FIFOs (see Section 1.1, Features, for FIFO size information) to buffer the 1394 data, thus preventing possible problems due to bus latency. This also ensures that the device can transmit and receive sustained maximum-size isochronous or asynchronous data payloads at S800.

The TSB83AA22C LLC section implements other performance enhancements to improve overall performance of the device, such as: a highly tuned physical data path for enhanced SBP-2 performance, physical post writing buffers, multiple isochronous contexts, and advanced internal arbitration. The TSB83AA22C LLC section also implements hardware enhancements to better support digital video (DV) and MPEG data stream reception and transmission. These enhancements are enabled through the isochronous receive digital video enhancements register at TI extension offset A80h (see Section 6.3.4, Isochronous Receive Digital Video Enhancements Register). These enhancements include automatic time stamp insertion for transmitted DV and MPEG-formatted streams and common isochronous packet (CIP) header stripping for received DV streams. The CIP format is defined by the IEC 61883-1:1998 specification. The enhancements to the isochronous data contexts are implemented as hardware support for the synchronization timestamp for both DV and audio/video CIP formats. The TSB83AA22C device supports modification of the synchronization timestamp field to ensure that the value inserted via software is not stale - that is, less than the current cycle timer when the packet is transmitted.

The TSB83AA22C performance and enhanced throughput make it an excellent choice for today's 1394 PC market; however, the portable, mobile, and even today's desktop PCs power management schemes continue to require devices to use less and less power, and Texas Instrument's 1394 product line has continued to raise the bar by providing the lowest-power 1394 devices in the industry. The TSB83AA22C device represents the next evolution of Texas Instruments commitment to meet the challenge of power-sensitive applications. The TSB83AA22C device has ultralow operational power requirements and intelligent power management capabilities that allow it to conserve power autonomously based on the device usage. The TSB83AA22C LLC section fully supports D0, D1, D2, and D3hot/cold power states as specified in the PC 2001 Design Guide requirements and the PCI Power Management Specification. PME wake event support is subject to operating system support and implementation. As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable.

The PCI configuration header is accessed through configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility. Furthermore, the TSB83AA22C LLC section is fully compliant with the latest PCI Local Bus Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394b-2002, IEEE Std 1394a-2000, and 1394 Open Host Controller Interface Specification. The TSB83AA22C Phy section provides the digital and analog transceiver functions needed to implement a two-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB83AA22C is powered by multiple voltage supplies, 3.3-V supplies for I/O and the LLC section, and a core voltage supply for the Phy section. The core voltage supply is supplied to the PLLVDD_CORE and DVDD_CORE terminals in accordance with the requirements in the recommended operating conditions.

The PLLVDD_CORE terminals must be separated from the DVDD_CORE terminals, the PLLVDD_CORE terminals are decoupled with 1-F and smaller decoupling capacitors, and the DVDD_CORE terminals separately decoupled with 1-F and smaller decoupling capacitors. The separation between DVDD_CORE and PLLVDD_CORE can be implemented by separate power supply rails, or by a single power supply rail, where the DVDD_CORE and PLLVDD_CORE are separated by a filter network to keep noise from the PLLVDD_CORE supply. In addition, REG_EN must be asserted low to enable the internal voltage regulator for the LLC section. If REG_EN is not pulled low, the a 1.8-V power rail must be applied to the REG18 pins.

The TSB83AA22C requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbps (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream. To ensure that the TSB83AA22C conforms to the IEEE Std 1394b-2002 standard, the BMODE terminal must be asserted.