TSB81BA3

· Fully Supports Provisions of IEEE P1394b Revision 1.33+ at 1-Gigabit Signaling Rates
· Fully Supports Provisions of IEEE 1394a−2000 and 1394−1995 Standard for High Performance Serial Bus
· Fully Interoperable With Firewire, i.LINK, and SB1394, Implementation of IEEE Std 1394
· Provides Three Fully Backward Compatible, (1394a−2000 Fully Compliant) Bilingual P1394b Cable Ports at up to 800 Megabits per Second (Mbits/s)
· Provides Three 1394a−2000 Fully Compliant Cable Ports at 100/200/400 Mbits/s
· Full 1394a−2000 Support Includes: − Connection Debounce − Arbitrated Short Reset − Multispeed Concatenation − Arbitration Acceleration − Fly-By Concatenation − Port Disable/Suspend/Resume − Extended Resume Signaling for Compatibility With Legacy DV Devices
· Power-Down Features to Conserve Energy in Battery Powered Applications
· Low-Power Sleep Mode
· Fully Compliant With Open Host Controller Interface (HCI) Requirements
· Cable Power Presence Monitoring
· Cable Ports Monitor Line Conditions for Active Connection to Remote Node
· Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and 1394a−2000 Features
· Data Interface to Link-Layer Controller Pin Selectable From 1394a−2000 Mode (2/4/8 Parallel Bits at 49.152 MHz) or 1394b Mode (8 Parallel Bits at 98.304 MHz)
· Interface to Link-Layer Controller Supports Low Cost TI Bus-Holder Isolation
· Interoperable With Link-Layer Controllers Using 3.3-V Supplies
· Interoperable With Other 1394 Physical Layers (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies
· Low Jitter, External Crystal Oscillator Provides Transmit and Receive Data at 100/200/400/800 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz and 98.304 MHz
· Separate Bias (TPBIAS) for Each Port
· Low Cost, High Performance 80-Pin TQFP (PFP) Thermally Enhanced Package
· Software Device Reset (SWR)
· Fail-Safe Circuitry Senses Sudden Loss of Power to the Device and Disables the Ports to Ensure That the TSB81BA3 Does Not Load the TPBIAS of Any Connected Device and Blocks any Leakage From the Port Back to Power Plane
· The TSB81BA3 Has a 1394a−2000 Compliant Common-Mode Noise Filter on the Incoming Bias Detect Circuit to Filter Out Cross-Talk Noise
· The TSB81BA3 Is Port Programmable to Force 1394a Mode to Allow Use of 1394a Connectors (1394b Signalling Must Not Be Put Across 1394a Connectors or Cables)

The TSB81BA3 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB81BA3 is designed to interface with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It may also be connected cable port to cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.

 The TSB81BA3 is powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-1.8 and DVDD-1.8 terminals to the requirements in the recommended operating conditions. The PLLVDD-1.8 terminals must be separated from the DVDD-1.8 terminals, the PLLVDD-1.8 terminals are decoupled with 1 F and smaller decoupling capacitors, and the DVDD-1.8 terminals separately decoupled with a 1 F and smaller decoupling capacitors. The separation between DVDD-1.8 and PLLVDD-1.8 may be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-1.8 and PLLVDD-1.8 are separated by a filter network to keep noise from the PLLVDD-1.8 supply.

The TSB81BA3 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The external clock drives an internal phase-locked loop (PLL), which generates the required reference signal. This reference signal provides the clock signals that control transmission of the outbound encoded information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two devices and is used for resynchronization of the received data when operating the PHY-link interface in compliance with the IEEE 1394a−2000 standard. A 98.304-MHz clock signal is supplied to the associated LLC for synchronization of the two devices when operating the PHY-link interface in compliance with the IEEE P1394b standard. The power down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

 Data bits to be transmitted through the cable ports are received from the LLC on 2, 4, or 8 parallel paths (depending on the requested transmission speed and PHY-link interface mode of operation). They are latched internally, combined serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbits/s (referred to as S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.

The PHY-link interface can follow either the IEEE 1394a−2000 protocol or the IEEE 1394b−2002 protocol. When using a 1394a−2000 LLC such as the TSB12LV26, the BMODE terminal must be deasserted. The PHY-link interface then operates in accordance with the legacy 1394a−2000 standard. When using a 1394b LLC such as the TSB82AA2, the BMODE terminal must be asserted. The PHY-link interface then conforms to the P1394b standard.

The cable interface can follow either the IEEE 1394a−2000 protocol or the 1394b protocol on all ports. The mode of operation is determined by the interface capabilities of the ports being connected. When any of the three ports is connected to a 1394a−2000 compliant device, the cable interface on that port operates in the 1394a−2000 data-strobe mode at a compatible S100, S200, or S400 speed. When a bilingual port is connected to a 1394b compliant node, the cable interface on that port operates per the P1394b standard at S400B or S800 speed.