TSB82AA2B

Features: ` Single 3.3-V Supply (1.8-V Internal Core Voltage With Regulator)` 3.3-V and 5-V PCI Signaling Environments` Serial Bus Data Rates of 100M Bits/s, 200M Bits/s, 400M Bits/s, and 800M Bits/s` Physical Write Posting of up to Three Outstanding Transactions` Serial ROM or Boot ROM Interface ...

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SeekIC No. : 004529213 Detail

TSB82AA2B: Features: ` Single 3.3-V Supply (1.8-V Internal Core Voltage With Regulator)` 3.3-V and 5-V PCI Signaling Environments` Serial Bus Data Rates of 100M Bits/s, 200M Bits/s, 400M Bits/s, and 800M Bits/...

floor Price/Ceiling Price

Part Number:
TSB82AA2B
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

` Single 3.3-V Supply (1.8-V Internal Core Voltage With Regulator)
` 3.3-V and 5-V PCI Signaling Environments
` Serial Bus Data Rates of 100M Bits/s, 200M Bits/s, 400M Bits/s, and 800M Bits/s
` Physical Write Posting of up to Three Outstanding Transactions
` Serial ROM or Boot ROM Interface Supports 2-Wire Serial EEPROM Devices
` 33-MHz/64-Bit and 33-MHz/32-Bit Selectable PCI Interface
` Multifunction Terminal (MFUNC Terminal 1):
PCI_CLKRUN Protocol Per the PCI Mobile
Design Guide
General-Purpose I/O
CYCLEIN/CYCLEOUT for External Cycle
Timer Control for Customized
Synchronization
` PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency:
Transmit FIFO-5K Asynchronous
Transmit FIFO-2K Isochronous
Receive FIFO-2K Asynchronous
Receive FIFO-2K Isochronous
` D0, D1, D2, and D3 Power States and PME Events Per the PCI Bus Power Management Interface Specification
` Programmable Asynchronous Transmit Threshold
` Isochronous Receive Dual-Buffer Mode
` Out-of-Order Pipelining for Asynchronous Transmit Requests
` Register Access Fail Interrupt When the PHY SYSCLK Is Not Active
` Initial Bandwidth Available and Initial Channels Available Registers
` Digital Video and Audio Performance Enhancements
` Fabricated in Advanced Low-Power CMOS Process
` Packaged in 144-Terminal LQFP (PGE)



Description

The TSB82AA2B OHCI-Lynx™ Controller is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today's 1394 bus designs. The TSB82AA2B  evice is capable of exceptional 800M bits/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses.

The TSB82AA2B device also provides  utstanding ultra-low power operation and intelligent power management capabilities. The device provides the IEEE 1394 link function and is compatible with 100M bits/s, 200M bits/s, 400M bits/s, and 800M bits/s serial bus data rates.

The TSB82AA2B improved throughput and increased bandwidth make it ideal for  oday's high-end PCs and open the door for the development of S800 RAID- and SAN-based peripherals. The TSB82AA2B OHCI-Lynx Controller operates as the interface between a 33- Hz/64-bit or 33-MHz/32-bit PCI local bus and a compatible 1394b PHY-layer device (such as the TSB81BA3 device) that is capable of supporting serial data rates at 98.304M, 196.608M, 393.216M, or 786.432M bits/s (referred to as S100, S200, S400, or S800 speeds, respectively). When acting as a PCI bus master, the  SB82AA2B device is capable of multiple cacheline bursts of data, which can transfer at 264M bytes/s for 64-bit  ransfers or 132M bytes/s for 32-bit transfers after connecting to the memory controller.




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