TSB12LV42

• Complies with IEEE 1394-1995 Standard
• Transmits and Receives Correctly Formatted 1394 Packets
• Supports SD-DVCR (DV) Formatted Isochronous Data Transfer
• Supports Isochronous Data Transfer
• Cycle Master (CM), Isochronous Resource Manager (IRM) and Bus Manager(BM) Capable
• Generates and Checks 32-Bit CRC
• Detects Lost Cycle-Start Packets
• 8K-Byte Bulky Data Interface (BDIF) for DV, Isochronous, and Asynchronous Data Transfer
• Multimode BDIF programmable for bytewide and memory mapped modes (independent for RX and TX)
• Implements a 256-Byte Control FIFO (Control FIFO) and an 8K-Byte Bulky Data FIFO
• 8K-Byte BDIF FIFO Implements Six Independent Logical FIFOs for DV, Isochronous, and Asynchronous Data Receive and Transmit through the BDIF
• Performs Bulky Asynchronous FIFO Packet Retry for Transmit (up to 256 Retries with Intervals  Up to 256 × 125 ms)
• 256-Byte Control FIFO for Control Packets
• Interfaces Directly to 100-Mbits/s and 200-Mb/s Physical Layer Devices Conforming to Annex J of 1394-1995
• Chip Control with Directly Addressable Configuration Registers (CFRs)
• Interrupt Driven to Minimize Host Polling
• Multimode 8-/16-Bit Microcontroller/Microprocessor Interface
• Supports 16-Bit Width Timestamp Offsets for DV Receive and Transmit.
• Optimized Pinout for Easy Board Layout
• Includes Texas Instruments Bus Holder Circuitry for Phy-Link Isolation
• Automatic CIP Header Insertion
• Automatic H0 DIF Block Insertion
• Automatic Empty Packet Insertion
• Supports both NTSC and PAL Formats
• Generates Output Frame Pulse

The features of TSB12LV42:

• Supports Provisions of IEEE 1394-1995 Standard for High-Performance Serial Bus
• Fully Interoperable with FireWireE Implementation of IEEE-1394 (1995)
• Interfaces Directly to Texas Instruments TSB11LV01 and TSB21LV03A Physical Layer Devices (100/200 Mbits/s)
• Single 3.3-V Supply Operation with 5-V Tolerance using 5-V Bias Terminals.
• High-Performance 100-Pin PZ (S-PQFP-G100) Package
• Multi-Microcontroller/Microprocessor Interface Supports TMS320AV7xxx, 680xx, 650x, 80x86, Z8x Processors
• 64 Quadlet (256 byte) Control FIFO Accessed through Microcontroller Interface Supports Command/Status Operations
• 8K-Byte FIFO Supports Standard-Definition Digital-Video Cassette Recorder (SD-DVCR), Asynchronous, and Isochronous Modes
• Bus Reset Functions and Automatic IEEE-1394 Self-ID Verification
• Supports IEC61883 standard formats for transmitting SD-DVCR data over 1394.